Topology Optimized Architectures with Programmable Poisson's Ratio over Large Deformations

Topology Optimized Architectures with Programmable Poisson's Ratio over Large Deformations.

Topology optimized architectures are designed and printed with programmable Poisson's ratios ranging from -0.8 to 0.8 over large deformations of 20% or more.

optimized reversible programmable logic array (pla)

reversible logic circuits have found emerging attentions in nanotechnology,optical computing, quantum computing and low power design. a programmablelogic array (pla) is a universal circuit which is used to implement combinationallogic circuits. the main part of a pla is its and array. in this study we propose twotypes of optimized reversible programmable logic array (rpla) circuits. the firstty...

Power optimized programmable embedded controller

Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor’s power. In this work clock gating technique is applied to optimize the power of fully programmable Embedded Controller (PEC) employing RISC...

Flexible Circuits and Architectures for Ultralow Power A programmable gate array optimized for ultralow-power operation

| Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ...

Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits